An industrial Ethernet module PCBA should not pass production because one link LED turns on. Manufacturing acceptance needs to prove that the released PHY configuration, clocks, magnetics, connector path, programmed identity and required traffic modes operate together with controlled evidence.
For example, the OEM must first define which Ethernet behavior belongs to the module and which belongs to the final equipment. A contract manufacturer can build and screen the released hardware, program controlled content and run an approved link and packet test. It should not invent latency, redundancy, EMC or protocol limits that were never provided by product engineering.
In addition, this guide focuses on the physical Ethernet path and repeatable production evidence. The wider GNS article on an industrial Ethernet deployment checklist addresses network planning after equipment is installed. Here, the question is whether each manufactured module matches the released hardware, firmware and port-test baseline before it reaches that network.
Freeze the industrial Ethernet module PCBA baseline
First, start with a one-page definition for each populated port. State the required speed, auto-negotiation behavior, duplex mode, PHY part and revision, MAC or processor interface, magnetics arrangement, connector, shield and chassis treatment, cable category, isolation requirement, PoE relationship where applicable and expected operating environment. Identify whether the module is a single-port endpoint, dual-port line device, switch module or part of a larger controller.
Next, separate physical Ethernet from the application protocol. A module may carry ordinary TCP/IP traffic, time-sensitive traffic or an industrial protocol, but the physical path still depends on power, clock, reset, straps, PHY-to-MAC timing, differential pairs, magnetics and the cable interface. Production testing should name which layer is being verified so a successful application message does not hide an untested speed or port.
Also, Release a controlled block diagram and port map. Connect every external connector to its PHY channel, magnetics, protection, shield path, status indicators and test access. If one PCB supports alternative PHYs, connectors or port counts, create a population matrix that also identifies the correct firmware, strap values, label and test recipe. An unpopulated second port should be recorded as an approved variant, not silently skipped by the fixture.
What evidence supports the decision
First, define the boundary around the host interface. RGMII, RMII, MII, SGMII or another interface can have different voltage, clock and timing requirements. State which device supplies the clock, which delay settings are implemented in silicon or PCB routing and which register values are expected after boot. These inputs determine what can be inspected structurally and what must be confirmed through register readback or traffic.
In addition, the GNS industrial electronics page provides application context, while the production equipment PCBA page covers equipment-level use. A live module still needs its own cable, topology, timing, temperature and acceptance inputs.
A released port baseline connects every physical Ethernet path to its assembly option, configuration and production evidence. Use a matrix like the following before DFM and fixture design begin.
For example, this table should remain synchronized with the schematic, BOM, layout, firmware release and test program. If an engineering change alters one row, the team can identify which assembly check, fixture step and regression test must change instead of treating the module as one undifferentiated network function.
Protect the PHY magnetics and connector signal path
First, review the complete path from the host interface to the cable. Confirm differential impedance, pair assignment, length and skew rules, reference planes, return-path continuity, via transitions, spacing from noisy power nodes and the relationship among PHY, magnetics and connector. Verify that the released stack-up matches the impedance model used during layout.
For example, the official TI DP83867E product resources include an Ethernet PHY PCB layout checklist and related timing material. These resources show why placement, return paths, clocks and host-interface timing need deliberate review. They are technical references, not universal limits for an OEM module.
Also, Magnetics and protection parts require more than reference-designator presence. Control the exact manufacturer part number or approved alternate, orientation, center taps, terminations, common-mode components, isolation rating and package. Check that protection devices are located and oriented according to the released design and that shield or chassis connections are not accidentally tied to circuit ground through solder, hardware or an unapproved component.
For example, Connector assembly adds mechanical failure modes. Inspect keying, pin-one orientation, coplanarity, solder fill, shield-tab joints, retention features and enclosure alignment. Large shielded connectors can affect paste release, reflow support and secondary soldering. The process plan should state whether the connector is reflowed, selectively soldered or installed manually and where it receives inspection.
However, AOI can confirm visible population, polarity and solder features, but it cannot prove differential impedance, transformer behavior, PHY timing or packet integrity. X-ray may help where joints are hidden, yet it also cannot replace a link and traffic test. Write inspection criteria around the actual package and joint, then connect each structural check to the risk it controls.
Inspection follows the released PHY-to-connector path and checks the components and joints that functional traffic alone may not localize. Control clocks straps firmware and MAC identity
Many Ethernet PHYs sample configuration straps during reset. A wrong resistor value, unapproved pull network, assembly contamination or host pin state can select an unintended address, interface voltage, clock mode or negotiation option. Record which straps are populated, their tolerance, when they are sampled and the expected PHY register state after startup.
Define oscillator or crystal part numbers, load components, placement, frequency tolerance and test method. If the host supplies a reference clock, specify its source and startup relationship. Production may verify clock presence or frequency at a protected test point, but the OEM should decide acceptable loading and probe method so the measurement does not disturb the circuit.
Programming should bind hardware revision, bootloader, application image, PHY driver settings and test recipe. Store a checksum or signed version reference and verify critical configuration through readback. A generic boot message is insufficient when the same image can run with several PHY addresses, delay settings, port counts or industrial protocol options.
MAC addresses require controlled ownership and allocation. State who supplies the address block, how the station requests an unused identity, where it is written, how duplicates are prevented and what happens to failed or scrapped units. The release record should connect MAC address, hardware revision, programmed content and port-test result without exposing unrelated credentials or keys.
Include reset and recovery behavior. Verify the approved power-on sequence, reset duration, link initialization and recovery after a controlled cable disconnect or power interruption. If the product requires a maximum reconnect time or watchdog response, engineering must release the numerical limit and test conditions. The factory should not turn an observed prototype time into an acceptance specification.
Build a fixture that exercises the complete port
A practical fixture begins with protected power, module identification and contact self-check. It should use production-representative connectors or replaceable cable adapters, a known peer device, controlled link settings and a stable traffic source. Where pogo pins access programming, MDIO or diagnostics, keep them away from critical differential routing and document their electrical effect.
Use loopback deliberately. The Microchip LAN9252 data sheet describes near-end and connector loopback modes. A near-end loopback can exercise substantial digital PHY circuitry, while connector loopback extends coverage through the external cable-side path. Neither mode automatically proves every magnetics, EMC, timing or application requirement, so the test record must identify which loop was used.
For each required port, check supply current and rails, reset, clock state, PHY identifier and key registers before traffic. Establish link with a defined peer and cable, record negotiated speed and duplex, then transmit and receive a controlled packet set. Capture packet counts and relevant error counters. If the module supports multiple mandatory speeds, define which are tested on every unit and which are covered by validation or sampling.
What proves the released route
Test the physical connector that will ship. An internal digital loopback can pass while a wrong transformer orientation, connector joint or pair path remains defective. Conversely, a cable test can fail because the fixture connector or peer is worn. Fixture self-test, replaceable interconnects and a known reference module help distinguish a production defect from a test-system defect.
If the module carries a real-time industrial protocol, production can exercise a controlled handshake after the physical link passes. Keep that transaction small and deterministic. Protocol conformance, network loading, synchronization accuracy and system interoperability belong to separate validation unless the production specification provides explicit cases and limits.
The production fixture verifies the released PHY state, cable-side link, negotiated mode, packet transfer and defined recovery behavior. Judge packet evidence instead of a green link light
A link LED answers a narrow question: the PHYs detected enough signaling to report link. It does not show whether the correct mode was negotiated, whether packets pass without error, whether the MAC address is unique or whether the module recovers correctly. Production acceptance should collect the smallest data set that detects the defined manufacturing risks.
Record the port, peer, cable or fixture revision, requested mode, negotiated mode, transmitted and received packet counts, CRC or frame errors where available, link interruptions, current and final result. Use numerical limits only when engineering has approved the test duration, packet size, traffic pattern and acceptable errors. Zero observed errors in a short run is evidence for that run, not a lifetime reliability claim.
Define retry rules before launch. A failed link should trigger checks for fixture contact, cable, peer status and module power without erasing the first result. If a second attempt is allowed, retain both outcomes and the reason. Repeated retries that eventually produce PASS are a process signal that requires review, not normal production behavior.
When the shipment decision reopens
The following coverage table keeps structural, functional and validation evidence separate.
When a required risk has no production test, state the gap and the alternative evidence. It may be controlled layout, approved materials, sample measurement, validation correlation or a system-level check. An explicit exclusion lets engineering decide whether the residual risk is acceptable.
Separate production screening from product validation
Every-unit production testing should be safe, repeatable and fast enough for the approved volume. Product validation can use longer cables, temperature corners, several peer devices, heavy traffic, timing analysis, EMC, surge, ESD and fault injection. Mixing these layers can either make production impractical or leave validation incomplete.
Define how the layers correlate. A production connector-loop test may screen open paths and gross PHY faults. Validation may establish that the released layout, magnetics, protection and enclosure satisfy specified immunity and emissions tests. Periodic audits or change-triggered samples can confirm that the manufacturing process remains represented by the validated design.
Industrial Ethernet features such as time synchronization, redundancy and deterministic cycle behavior need system-level conditions. If the module claims a numerical timing result, the OEM should define clock sources, network topology, traffic, cable, software version and instrumentation. The EMS provider can execute an approved procedure but should not infer a performance claim from a basic ping test.
Environmental and mechanical validation also belong to the product baseline. Connector loading, vibration, thermal cycling, contamination, coating, enclosure grounding and cable strain can affect the Ethernet path. Identify which controls apply to the bare PCBA and which require the final housing or equipment assembly.
The GNS quality assurance page provides process-control context. Project documentation should still name the exact inspection classes, sample plans, electrical limits, records and approval responsibilities used for this module.
Release NPI with change and traceability controls
First article should reconcile PCB revision, stack-up, material identity, PHY and magnetics options, connector orientation, strap values, clocks, programmed content and labels before extended testing. Review deviations before the traffic run. A correct sample produced through an undocumented manual correction is not a repeatable NPI result.
The pilot build should use production-intent stencil, tooling, programming, MAC allocation, fixtures, cables, peers, test software and data capture. Audit at least one record from incoming material through assembly, inspection, programming and every required port. Confirm that another operator or shift can reproduce the setup and interpret a failure.
Changes should be assessed by mechanism. A PHY replacement can affect straps, timing, driver settings and EMC. Magnetics can affect isolation, return loss and cable performance. A connector can change pinout, shield, soldering and enclosure fit. Firmware can change negotiation, delay settings and error reporting without altering the PCB. The change package should identify affected evidence rather than applying one generic retest.
What evidence supports the decision
Retain hardware and firmware effectivity, critical material lots, inspection, programmed identity, test recipe, fixture revision, per-port results, repair, deviations and final release. The record may be serial-based or lot-based according to product risk, but it should let quality teams determine which units share the affected configuration.
Long-life industrial modules also need recoverable programming and test capability. Preserve approved firmware, PHY configuration, address allocation rules, fixture drawings, peer settings, replacement cables and known references. Review component lifecycle changes before an urgent purchase forces a technical decision into the production schedule.
The release record connects the physical module, programmed identity, PHY configuration and per-port test result. For an EMS review, submit Gerber and fabrication data, stack-up and impedance rules, BOM and approved sources, centroid, drawings, port matrix, PHY configuration, firmware, MAC allocation method, required link modes, traffic limits, quantities and equipment environment. Ask the supplier to return DFM findings, fixture concept, test coverage, exclusions and evidence format before the pilot build.
Conclusion
An industrial Ethernet module PCBA is ready for production when its physical port, configuration, identity and traffic evidence are controlled as one release. The essential actions are freezing the port baseline, preserving the PHY-to-connector signal path, controlling straps and firmware, testing the complete cable-side interface and recording more than a link indication.
Keep production screening distinct from EMC, timing and interoperability validation, but document how the layers cover the released risks. When a PHY, magnetics, connector, stack-up or firmware change occurs, review the affected mechanism and repeat the evidence that could change. This approach gives engineering, sourcing and quality teams a recoverable basis for accepting the pilot and future builds.
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FAQ
What files are needed for an industrial Ethernet module PCBA quote?
Provide fabrication data, BOM and approved sources, centroid, assembly drawings, stack-up and controlled-impedance requirements, Ethernet port map, PHY configuration, firmware, MAC address rules, connector details, test limits, quantities and the intended equipment environment.
Does an Ethernet link LED prove that the module passed production test?
No. A link LED does not confirm the correct speed, duplex mode, PHY register state, packet integrity, magnetics path, MAC identity, error counters or recovery behavior. Production acceptance should exercise the released link modes and record traffic results against defined limits.
Should every module be tested at every supported Ethernet speed?
The OEM should define coverage from product risk and the released use case. Every required production mode should have justified evidence, but lower-risk or rarely used modes may be covered by validation, sampled tests or structural checks when the correlation and exclusions are documented.
How should a PHY or magnetics change be qualified?
Review electrical compatibility, pinout, straps, clocking, interface timing, layout, impedance, isolation, return loss, link modes, EMC and firmware assumptions. Run controlled first-article and regression tests, approve the evidence and record the effective hardware and software revisions before production use.
