QFN and QFP assembly should not use one package rule merely because both devices have terminals around four sides. A QFP normally presents formed leads beyond the package body, so lead condition and much of the solder joint can be viewed. A QFN is a bottom-termination component: its perimeter terminals and any exposed center pad connect beneath the body, where direct visual access is limited.
That difference changes land-pattern review, paste design, placement controls, defect visibility, inspection evidence, rework, and the buyer’s release decision. It does not mean that every QFP can be accepted by appearance or that every QFN needs the same X-ray limit.
The release needs a reproducible evidence chain: the OEM owns the product definition and acceptance requirements, while the EMS provider owns executable controls, records, and exception escalation.
Define the package and product requirements
Start with the exact manufacturer part number and package drawing. Family names such as QFN, DFN, LQFP, TQFP, or “48-pin QFP” do not fully define body size, pitch, terminal geometry, exposed-pad construction, moisture sensitivity, coplanarity limits, or the recommended land pattern.
Distinguish termination and inspection access
A QFP’s formed leads extend outside the body. This generally gives optical systems access to lead presence, alignment, bridging, and visible solder features, subject to pitch, view angle, component height, lighting, program validation, and the contracted acceptance criteria. Bent leads, coplanarity, toe position, and solder-volume variation can still create conditions that a single top view does not fully characterize.
A QFN has planar terminations under the body, with or without wettable side flanks. The January 2026 IPC-7093B table of contents and scope identifies QFN, DFN, SON, and LGA as bottom-termination components and covers their design, materials, assembly, inspection, repair, quality, and reliability issues. That scope is the correct starting point: package implementation is a connected system, not an X-ray-only decision.
Record whether the selected QFN offers wettable flanks and what the component supplier says those flanks can support. A visible side fillet can add inspection evidence, but it does not expose the complete bottom interface or prove the condition of an exposed center pad.
Reconcile package, land, and assembly data
Cross-check the BOM manufacturer part number, approved source, package drawing, CAD footprint, land pattern, solder-mask definition, paste layer, centroid data, polarity or pin-one mark, assembly drawing, and variant rules. Confirm that the package dimensions and terminal numbering in the library match the released component data.
For QFN devices, review the perimeter lands, exposed-pad geometry, thermal vias, via treatment, solder-mask boundaries, keep-outs, and the electrical or thermal function of the center pad. For QFP devices, review lead pitch, heel and toe land geometry, solder-mask web, nearby copper, courtyard, component height, and access for inspection and rework.
IPC-7351B provides the industry’s generic requirements for surface-mount land patterns. Apply the licensed revision with the exact package drawing and product constraints. A library match alone does not qualify the actual source, PCB finish, stencil, paste, and process.
Use the GNS BOM and Gerber input checklist to reconcile the released manufacturing files before stencil and program generation.
Assign acceptance and evidence ownership
Define the contract, customer specification, product class, standard revision, component instructions, and approved deviations. Name who releases the footprint, stencil, profile, inspection and test programs, first article, rework instruction, and production route.
The supplier can propose an aperture, profile, X-ray method, or repair route. The OEM decides whether it satisfies product thermal, electrical, mechanical, reliability, regulatory, and customer requirements. Quality defines the evidence and authority for exceptions; a quotation assumption is not a product requirement.
Before build release, log each open issue with its package, reference designators, input revision, risk, action, evidence, owner, due gate, disposition, and approval.
Release lands, stencil, paste, and placement inputs
The released stencil, paste, support and program must match the exact package and PCB data. Paste transfer and placement create the joint geometry that later inspection tries to evaluate. Do not wait for a finished-board X-ray or functional failure to discover that the package, stencil, and PCB definitions disagreed.
Control QFP lead and paste conditions
For a fine-pitch QFP, review stencil thickness, aperture geometry, paste type, board support, print alignment, release behavior, paste deposit repeatability, placement accuracy, lead coplanarity, and reflow self-alignment. The design must balance the risks of bridging and excessive solder against insufficient solder and open joints.
Define incoming and setup checks for lead damage, tray or reel orientation, package identity, pin-one marking, and nozzle selection. Handling should not deform leads. Placement force and board support should not damage the package, smear paste, or bow the panel.
Set print-inspection or first-off evidence for the high-risk lead rows. If the project uses solder paste inspection, document the measured features, program revision, limits, alarm reaction, and trace boundary. If it uses another verification method, state its coverage and sampling rather than claiming implied control.
Segment QFN perimeter and exposed-pad deposits
The QFN paste layer should be released from the exact device and PCB construction. Review perimeter-terminal apertures separately from the exposed-pad pattern. For the center pad, consider the supplier recommendation, pad dimensions, thermal-via layout and filling or capping, paste escape paths, stencil thickness, paste behavior, component standoff, void expectations, and product thermal and electrical needs.
Texas Instruments’ current QFN and SON PCB Attachment guide covers land patterns, solder mask, stencil design, reflow, inspection, and rework for the packages within its scope. Analog Devices’ AN-772 LFCSP guide likewise connects package construction, footprint, stencil, assembly, inspection, and reliability guidance. Use the data for the selected part and application; do not turn a vendor example into a universal paste percentage.
Preserve the released paste Gerber or aperture data, stencil identifier, thickness, step areas, surface treatment where used, supplier, inspection record, and approved revision. If the exposed-pad pattern changes, reopen the evidence affected by solder volume, standoff, void behavior, thermal performance, and reliability.
The GNS guide to SMT solder-paste stenciling explains the underlying print process. This release gate adds package-specific configuration, evidence, and approval.
Verify orientation, support, and program data
Reconcile the centroid rotation and machine library with the package drawing and a known physical sample. Pin-one marks can be subtle or differ between body, tray, reel, and drawing views. Record the first-off orientation evidence and the reference designators checked.
Select nozzles and vision settings for the actual body and surface. Verify pickup position, package recognition, terminal or body reference, placement height, force, and support. For QFPs, protect leads from contact and deformation. For QFNs, prevent pickup or placement conditions that damage the body, disturb paste, or create tilt.
The table below is a release gate, not a set of universal dimensions.
Input gate
Evidence required before build
Package
Exact MPN, source, package drawing, terminal geometry, MSL, finish, and pin-one definition
PCB
Released land, mask, paste, thermal-via, finish, panel, support, and keep-out data
Stencil
Identifier, revision, thickness, apertures, step areas, paste, cleaning rule, and approval
Program
Released library, centroid, rotation, nozzle, vision, height, force, and first-off check
Criteria
Contracted standard, product-specific limits, supplier guidance, deviations, and owners
Trace
PCB, component, stencil, paste, program, machine, time, panel, and unit or lot identity
Control reflow, moisture, and first-article evidence
A released oven recipe must be supported by a representative populated-assembly profile. A recipe name is not a profile. The release must show that the populated assembly, materials, packages, and board construction experienced an acceptable thermal process.
Profile the representative populated assembly
Confirm the profile on a representative populated panel using production paste, support, conveyor configuration, and oven. Select thermocouple locations for thermal mass, package risk, board edges, dense areas, shadowing, and expected hot and cold joints. Preserve attachment method, locations, equipment, recipe, belt speed, and result.
NXP’s surface-mount reflow guidance AN10365 covers PCB footprints, paste printing, reflow, inspection, repair, and component handling. Use package-specific supplier limits plus the paste and laminate data. Peak temperature, time above liquidus, ramp, soak, cooling, body temperature, and joint temperature answer different process questions.
Do not approve QFN voiding, QFP wetting, or product thermal behavior from the oven profile alone. The profile controls heat exposure; inspection and product verification evaluate different outputs.
Control MSL and cumulative heat exposure
Capture the moisture-sensitivity level and approved storage, dry-pack, floor-life, baking, and rework instructions for each affected package. Track exposure from package opening through placement, reflow, delay, second-side processing where applicable, inspection, and rework.
Define what happens when time or environmental limits are exceeded. The traveler should identify the material lot, exposure status, recovery action, and release authority. Avoid an undocumented “bake and use” decision.
Record cumulative thermal history where the board can receive multiple reflow passes, local rework, or repair. Confirm package and board limits before adding another heat cycle. Rework equipment settings cannot be copied between board thicknesses, copper distributions, adjacent components, or package sizes without review.
Preserve a package-specific first article
The first article should demonstrate the released configuration and process. Record the effective PCB, BOM, package drawing, stencil, paste, placement program, profile, inspection, test, and acceptance revisions. Link results to the panel, unit, lot, traveler, or serial identity.
For QFPs, preserve orientation, lead condition, print and placement results, visible joint inspection, defect disposition, and electrical or functional results. For QFNs, preserve perimeter and exposed-pad print evidence, placement, profile identity, defined visible and X-ray evidence, electrical or functional results, and thermal verification when product risk requires it.
Document deviations, rework, substitutions, and repeated inspection. A final passing photo should not hide an unapproved correction.
Match inspection and test to package risks
Optical evidence is useful only for package features that the validated view can actually see. Inspection methods should be selected by feature, defect mechanism, accessibility, and product consequence. A capable machine does not create coverage unless the program, views, criteria, validation, sampling, and reaction rules are controlled.
Use optical evidence within its visibility boundary
For QFPs, visual inspection or AOI can evaluate visible lead position, polarity, gross alignment, bridging, and specified solder-joint features. Define the views and features used, the reference standard and revision, program validation, false-call handling, reviewer authority, and defect coding.
Fine pitch, body shadow, adjacent parts, lead geometry, solder-mask color, surface reflection, contamination, and camera angle can reduce visibility. A top-side image may show alignment while missing a heel condition. State the known boundary rather than reporting “AOI passed” as total joint proof.
For QFNs, optical inspection can verify package presence, orientation, alignment, and visible edge features. Wettable flanks may support additional visible evidence if the selected package and process are designed for them. Optical evidence still does not reveal the entire bottom termination or center-pad interface.
Define X-ray purpose and acceptance before use
X-ray can add defined hidden-joint evidence but cannot prove every electrical or reliability condition. X-ray can add evidence for hidden QFN features such as solder distribution, certain bridges, large void structures, or alignment, depending on board construction, package, view, resolution, image processing, and operator interpretation. It cannot by itself prove intermetallic quality, mechanical strength, electrical function, long-term reliability, or thermal performance.
Define the reference designators, inspected population or sampling plan, required views, machine and program, image retention, measurable features, acceptance source, escalation threshold, and review authority. If a percentage is used, identify exactly what area and projection it represents, how it is measured, and why it is valid for the product.
The GNS AOI, AXI, and ICT methods overview can help build a coverage matrix. Convert it into board-specific checks instead of choosing equipment by name.
Combine process, electrical, functional, and thermal proof
Electrical tests can identify opens, shorts, or accessible-network behavior within their fixture and program coverage. Functional tests can confirm selected product behavior under defined stimuli and limits. Neither method identifies every latent solder condition, and a passing power-on test does not reconstruct the process history.
For a thermally significant QFN exposed pad, define whether design analysis, temperature measurement, power cycling, environmental stress, or other product validation is required. Assign that decision to the product authority. The assembly supplier should provide the requested process and joint evidence, but should not invent a product thermal limit.
Create one coverage table that maps critical features to process evidence, inspection or test method, stage, population, criteria, record, owner, and escalation. Preserve known gaps.
Risk gate
Required release evidence
QFP leads
Incoming lead condition, print, placement, visible-joint views, criteria, defects, and disposition
QFN perimeter
Print and placement evidence, visible edge or flank checks where applicable, and hidden-joint plan
QFN center
Released paste and via design, profile, defined X-ray evidence, and thermal or electrical proof as required
Test
Controlled program and fixture, declared coverage, result, failure analysis, and retest record
Exception
Affected scope, containment, technical review, authority, work instruction, and post-work evidence
Release
First-article identity, complete record set, open-risk closure, approval, and repeat-build baseline
Control nonconformance, rework, and change
Hidden-joint packages and fine-pitch leads make uncontrolled repair especially costly. Define containment and rework evidence before the first defect occurs.
Contain the affected scope before disposition
When inspection or test finds a defect, stop or segregate the defined scope. Use component lot, PCB lot, stencil, paste lot, program, machine, lane, panel position, time window, operator, profile, inspection result, and traveler identity to determine what may be affected.
Separate a single handling event from a repeated process signature. Review related reference designators and boards where the same print, placement, reflow, or material condition was used. Preserve the original image, test result, defect code, and unit identity before work changes the evidence.
The Global Electronics Association’s 2024 notice for IPC J-STD-001J and IPC-A-610J explains that one document governs soldering processes and materials while the other addresses completed-assembly acceptance. Use the revisions named by the contract; an acceptable appearance does not cancel a process deviation.
Release qualified rework and retest
The rework instruction should identify package removal, site preparation, paste application, alignment, localized heating, temperature monitoring, board support, adjacent-part protection, cleaning, inspection, retest, and allowed thermal exposure. Equipment and profiles must suit the actual board and package.
For QFPs, control lead damage, pad lifting, solder bridges, residue, and adjacent-component disturbance. For QFNs, account for bottom-side alignment, center-pad paste, thermal-via behavior, hidden-joint inspection, and the difficulty of proving site preparation after removal.
Define whether the action is touch-up, rework, repair, use-as-is, or scrap, and use the proper authority. Update thermal history and traceability. Retest the functions and networks affected by both the original defect and the work performed.
Reopen gates when assumptions change
Create change triggers for the PCB, land pattern, solder mask, thermal vias, component source, package revision, terminal or lead geometry, finish, MSL, stencil, paste, placement library, nozzle, support, reflow equipment or recipe, inspection program, test coverage, repair route, acceptance criteria, and traceability fields.
For each trigger, define the review owner and evidence: document update, targeted first-off, new profile, inspection-program validation, first article, electrical or thermal validation, reliability work, or customer approval. A component source under the same customer line item may still alter package construction or manufacturing guidance.
Use the GNS manufacturing traceability checklist to confirm that the required identifiers and sample records exist before repeat orders. Traceability is useful only when it can connect a delivered unit to the effective inputs, process, inspection, test, deviations, and approvals.
CTA: Send the released BOM, PCB and panel data, package drawings, placement files, assembly drawing, stencil requirements, inspection and test criteria, and change rules for a controlled QFN and QFP assembly review.
Conclusion
QFN and QFP assembly is ready for repeat production only when package-specific risks are converted into controlled evidence. Reconcile the exact part and land data, release the stencil and placement configuration, profile the representative assembly, control moisture and thermal history, and preserve a first article that identifies what was actually built.
Use optical inspection where the QFP or package feature is genuinely visible. For hidden QFN interfaces, define what print evidence, X-ray, electrical test, functional test, and product thermal validation each contribute, including what they cannot prove. Do not replace that coverage plan with a universal paste percentage, void limit, or generic “AOI passed” statement.
Finally, contain defects before rework, qualify the rework and retest route, and reopen the relevant gate when a package, board, material, program, profile, inspection, or test assumption changes. The result is not merely a soldered component. It is a traceable release decision that the buyer and manufacturer can reproduce, review, and defend.
Request a QFN/QFP Assembly Review
FAQ
Can AOI alone release both QFN and QFP solder joints?
No. AOI can provide useful evidence for visible QFP leads and visible package or placement features, but most QFN terminations are under the package body. QFN evidence may require a controlled combination of print inspection, process records, external visual features where applicable, X-ray for defined internal conditions, and electrical, functional, or thermal verification. The project must state what each method covers and what it cannot prove.
Is one solder-paste coverage percentage suitable for every QFN exposed pad?
No. The released paste design must follow the exact component drawing and package guidance, land and via construction, stencil and paste capability, thermal and electrical needs, void criteria, board design, and validated process. A generic percentage cannot replace device-specific data or product evidence. Record the approved aperture design and the evidence used to release it.
What belongs in a QFN and QFP first-article record?
Identify the effective PCB, BOM, placement, drawing, package, stencil, paste, program, profile, inspection, test, and acceptance revisions. Preserve setup verification, print and placement evidence, reflow profile identity, moisture and thermal history where applicable, visible and hidden-joint inspection results, electrical or functional results, deviations, rework, approval, and the unit, panel, lot, or traveler identity linking the evidence to the build.
When should an approved QFN or QFP assembly process be reviewed again?
Reopen the release when PCB or thermal-via construction, land or mask data, package drawing, component source, terminal geometry, finish, MSL, stencil, paste, placement, support, reflow, inspection, test, repair, acceptance, or traceability assumptions change. Decide which proof must be repeated and who must approve it before production uses the new condition.
